In modern voltage regulator systems for microprocessor core voltage controlling, multi-phase control has been a popular control method for adapting high power density and high current slew rate requirements. However, conventional multi-phase control method is still insufficient to meet these ultra high load transient requirements in recent generations' voltage regulator (VR) specifications defined by Intel, especially during load application transient. Accordingly, an open-loop control mechanism called quick response was developed to overcome the undershoot problem. During load application transient, the quick response mechanism will instantaneously turn on all phases' upper gate (UG) to fully supply heavy load current demand, and the output voltage droop can therefore be controlled into correct load line specification. Even so, the quick response function still has some defects. For example, inaccurate turn-on or turn-off of quick response may result in unexpected ring back or second undershoot of output voltage.
FIG. 1 is a block diagram of an interleaving pulse width modulation (PWM) voltage regulator system with conventional quick response control scheme, which includes N phases, phase 1, phase 2, . . . , phase N, where N is a natural number, parallel connected between a power input VIN and a power output VOUT. Each phase has a power stage 10 connected to the power input VIN and power output VOUT, and a PWM comparator 12 to decide a pulse width modulation signal PWMj, j=1, 2, . . . , or N, for the power stage 10 of this phase. In order to generate the per-phase pulse width modulation signals PWM1, PWM2, . . . , PWMN, voltage divider resistors R1 and R2 divide the output voltage VOUT to generate a feedback signal VFB, an error amplifier 14 compensates the error between the feedback signal VFB and a reference signal VREF and provides an amplified error signal VCOMP into the positive inputs of each PWM comparator 12, and each PWM comparator 12 compares the error signal VCOMP with a ramp signal VRAMP to decide the pulse width modulation signal PWMj of the corresponding phase. Each of the power stages 10 is controlled by the pulse width modulation signal PWMj of the corresponding phase to switch one or more power switches thereof, so as to generate the phase currents IL1, IL2, . . . , ILN, whose combination is the load current ILOAD supplying for the load 16. The function of quick response is implemented by a quick response generation circuit 18 and per-phase combiners 20. The quick response generation circuit 18 monitors the error signal VCOMP to decide a quick response signal QR which triggers a quick response pulse when a load transient occurs. Each combiner 20 inserts the quick response pulse into the pulse width modulation signal PWMj of the corresponding phase. Alternatively, the quick response generation circuit 18 monitors the output voltage VOUT or the feedback signal VFB instead, in order to trigger the quick response pulse.
FIG. 2 is a simplified block diagram of a per-phase feedback control circuit extracted from FIG. 1 for detailed description about the conventional quick response control scheme. In order for particular distinction, the reference signals for the error amplifier 14 and the quick response comparator 22 are denoted by VREF1 and VREF2 respectively. The positive and negative inputs of a quick response comparator 22 receive the reference signal VREF2 and feedback signal VFB respectively, to decide the quick response signal QR. The input voltages of the quick response comparator 22, VREF2 and VFB, are so designed to meet the circumstance that under steady state operation, VREF2 will always be lower than VFB and hence the output of the quick response comparator 22 will always be zero. Therefore, the pulse width modulation signal PWM will always be determined only by the output of the PWM comparator 12 in steady state. Moreover, VREF2 is so designed to meet the circumstance that VREF2 will approach VFB, either VREF2 rising or VFB falling, during load application. When VREF2 is higher than VFB, the output QR of the quick response comparator 22 goes high and the output of the combiner 20 goes high according to the quick response pulse. Hence, during load application, the pulse width modulation signal PWM is determined not only by the output of the PWM comparator 12 but also by the output of the quick response comparator 22. In other words, the quick response pulse will be inserted into the normal pulse width modulation signal PWM and dominates the PWM pulse width during instant load application.
FIG. 3 is a timing diagram illustrating an operation mode of the conventional quick response control scheme in a four phase voltage regulator. At time t1, the load current ILOAD transits from IMIN to IMAX, and the output voltage VOUT of the voltage regulator drops accordingly. At the moment the output voltage VOUT drops, the quick response comparator 22 will assert the quick response signal QR to instantaneously turn on all the pulse width modulation signals PWM1-PWM4 of the interleaved phases to supply this high load current demand. At time t2, the quick response period ends and the per-phase inductor currents are raised to a higher level, but the delay of gate signal transmission and per-phase inductor current imbalance cause the output voltage VOUT to exhibit a period of ringback phenomenon 24. After time t2, the pulse width modulation signal PWM3 restarts its original PWM pulse and the subsequent PWM pulses will automatically adjust their pulse widths to regulate the output voltage VOUT to the desired level. However, the system will suffer a long period of current imbalance until the end of time t3. The time length of current imbalance depends on the quick response trigger point, quick response duration, inductor current level, restart point of the pulse width modulation signal PWM, . . . etc. This current imbalance phenomenon may cause unexpected ringback or short-term ringing of output voltage VOUT and hence increases the amount of output bulk or decoupling capacitors.
In order to resolve these defects of conventional quick response, a circuit and method of per-phase current balancing and pulse width adjustment of quick response is proposed. Altogether, the proposed new algorithm of quick response can achieve perfect adaptive voltage positioning (AVP) function without unnecessary undershoot or ringback of output voltage during load transient.